SH7710 Datasheet, PDF (907/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 25 Electrical Characteristics
25.3.2 Control Signal Timing
Table 25.6 Control Signal Timing
(Conditions: V_CCQ = V_CCQ-RTC = 3.0 to 3.6 V, V_CC = V_CC-PLL1 = V_CC-PLL2 = 1.4 to 1.6 V,
V Q = V = V Q-RTC = V -PLL1 = V -PLL2 = 0 V, T = –20 to 75°C)
SS
SS
SS
SS
SS
a
66.67 MHz*²
Item
Symbol
Min.
Max.
Unit Figure
RESETP pulse width
RESETP setup time*¹
RESETM pulse width
RESETM setup time
BREQ setup time
BREQ hold time
NMI setup time*¹
t
RESPW
t_RESPS
t_RESMW
t
RESMS
t
BREQS
t
BREQH
t
NMIS
20*³
—
20
—
20*⁴
—
10
—
1/2 t +10 —
cyc
1/2 t +3 —
cyc
10
—
t
25.12
cyc
ns
t_cyc
ns
25.14
25.13
NMI hold time
IRQ5 to IRQ0 setup time*¹
t_NMIH
t
IRQS
3
—
10
—
IRQ5 to IRQ0 hold time
BACK delay time
t_IRQH
t_BACKD
3
—
—
1/2 t_cyc+13
25.14
STATUS1, STATUS0 delay time
t_STD
—
18
IRQOUT delay time
t
—
1/2 t +12
IRQOTD
cyc
25.15
25.16
Bus tri-state delay time 1
t
0
30
BOFF1
25.14,
Bus tri-state delay time 2
t
0
30
BOFF2
25.15
Bus buffer-on time 1
t
BON1
0
30
Bus buffer-on time 2
t_BON2
0
30
Notes: t_cyc is the external bus clock cycle (B clock cycle).
1. RESETP, NMI, and IRQ5 to IRQ0 are asynchronous. Changes are detected at the
clock rise when the setup shown is kept. When the setup cannot be kept, detection can
be delayed until the next clock rises.
2. The upper limit of the external bus clock is 66.67 MHz.
3. In standby mode, t_RESPW = t_OSC2 (10 ms). When the crystal oscillation continues or the
clock multiplication ratio is changed in standby mode, t_RESPW = t_PLL1 (100 µs).
4. In standby mode, t = t (10 ms). When the crystal oscillation continues or the
RESMW
OSC2
clock multiplication ratio is changed in standby mode, RESETM must be kept low until
STATUS (0-1) changes to reset (HH).
Rev. 2.00 Dec. 07, 2005 Page 865 of 950
REJ09B0079-0200