SH7710 Datasheet, PDF (666/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
No.
Time Chart
Start
1
Set SIMDR, SISCR, SITDAR,
SIRDAR, SICDAR, and SIFCTR
2
Set SCKE bit in SICTR to 1
3
Start SCK_SIO clock transmission
4
Set FSE bit in SICTR to 1
5
Set TXE bit in SICTR to 1
6
TDREQ=1? ^No
Yes
7
Set SITDR
SIOF Settings
SIOF Operation
Set operating mode, serial clock,
slot positions for transmit/receive
data, slot position for control data,
and the upper limit value of FIFO
request
Set operation start for baud rate
generator
Output serial clock
Set the start for frame
synchronous signal
Set to enable transmission
Transmit frame
synchronous signal
Submit transmission
request
Set transmit data
8
Output SITDR contents from TXD_SIO
synchronously with SIOFSYNC
Transmit
Transfer
No
ended?
9
Yes
Clear TXE bit in SICTR to 0
End
Set to disable transmission
End transmission
Figure 17.9 Example of Transmission Operation in Master Mode
Reception in Master Mode: Figure 17.10 shows an example of settings and operation for master
mode reception.
Rev. 2.00 Dec. 07, 2005 Page 624 of 950
REJ09B0079-0200