SH7710 Datasheet, PDF (151/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Table 3.16 DSR Register Bits
Initial
Bits Bit Name Value
R/W
31 to —
12
All 0
R
11 to 9 TS2 to TS0 All 0
R/W
8
TC
0
R/W
7
GT
0
R/W
6
Z
0
R/W
Section 3 DSP Operating Unit
Function
Reserved Bits
These bits are always read as 0. The write value
should always be 0.
T Bit Status Selection
Specifies the operation result status to be set in the T
bit in the SR register if the TC bit is 1. If the S bit of
the SR register is set to 1, an overflow is detected.
000: Carry/borrow mode
001: Negative value mode
010: Zero mode
011: Overflow mode
100: Signed greater mode
101: Signed greater than or equal to mode
110: Reserved (setting prohibited)
111: Reserved (setting prohibited)
TC Bit
0: The T bit of the SR register is not affected by the
DSP instruction.
1: The T bit of the SR register changes according to
the TS bit of the DSR register while the DSP
instruction is executed. Note, however, the T bit
does not change during conditional DSP instruction
execution.
Signed Greater Bit
Indicates that the operation result is positive (except
0), or that operand 1 is greater than operand 2
1: Operation result is positive, or operand 1 is greater
than operand 2
Zero Bit
Indicates that the operation result is zero (0), or that
operand 1 is equal to operand 2
1: Operation result is zero (0), or operands are equal
Rev. 2.00 Dec. 07, 2005 Page 109 of 950
REJ09B0079-0200