SH7710 Datasheet, PDF (48/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 1 Overview and Pin Function
• Transfer data width: 32 bits
• Address space: 4 Gbytes
• On-chip FIFO (2-kbytes each for transmit/receive)
IP Security Accelerator (IPSEC):
• DES/Triple-DES encryption/decryption according to DES (Data Encryption Standard)
• Hash algorithm generation according to MD5 Message Digest Algorithm
• Hash algorithm generation according to SHA-1 Source Hash Standard
• On-chip DMAC dedicated for data transfer
• Interrupt request support
User debugging interface (H-UDI):
• Supports the E10A emulator
• Realtime branch trace
• 1-kbyte of on-chip RAM for executing the high-speed emulation program
Notes: 1. As the power supply is connected, power should always be supplied to all power
supplies even if only RTC operates.
2. +5 V I/O is not supported.
3. Magic Packet is the registered trademark of Advanced Micro Devices Inc.
Product Lineup:
Power supply voltage
Abbreviation
I/O
Internal
SH7710
3.3 V ± 0.3 V 1.5 V ± 0.1 V
Maximum
operating
frequency Type name
Package
200 MHz HD6417710BP/BPV 256-pin CSP
(BP-256H/HV)
HD6417710F/FV
256-pin HQFP
(FP-256G/GV)
Rev. 2.00 Dec. 07, 2005 Page 6 of 950
REJ09B0079-0200