SH7710 Datasheet, PDF (388/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
27
IWRWD2 0
R/W Idle Cycles for Another Space Read-Write
26
IWRWD1 1
25
IWRWD0 1
R/W Specify the number of idle cycles to be inserted after the
R/W ^{access to a memory that is connected to the space. The}
target access cycle is a read-write one in which continuous
accesses switch between different spaces.
000: No idle cycle inserted
001: 1 idle cycles inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
24
IWRWS2 0
R/W Idle Cycles for Read-Write in Same Space
23
IWRWS1 1
22
IWRWS0 1
R/W Specify the number of idle cycles to be inserted after the
R/W ^{access to a memory that is connected to the space. The}
target cycle is a read-write cycle of which continuous
accesses are for the same space.
000: No idle cycle inserted
001: 1 idle cycles inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
Rev. 2.00 Dec. 07, 2005 Page 346 of 950
REJ09B0079-0200