SH7710 Datasheet, PDF (674/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
1 frame
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
Lch.DATA
Slot No.0
Slot No.1
Slot No.2
Slot No.3
No bit delay
Setting: TRMD = 00 or 10, REDG = 0,
FL = 1101 (frame length: 64 bits)
TDLE = 1,
TDLA3 to TDLA0 = 0000, TDRE = 0, TDRA3 to TDRA0 = 0000,
RDLE = 1,
RDLA3 to RDLA0 = 0000, RDRE = 0, RDRA3 to RDRA0 = 0000,
CD0E = 0,
CD0A3 to CD0A0 = 0000, CD1E = 0, CD1A3 to CD1A0 = 0000
Figure 17.15 Transmission and Reception Timings (16-Bit Monaural Data (1))
16-bit Stereo Data (1): L/R method, rising edge sampling, slot No.0 used for left channel data,
slot No.1 used for right channel data, frame length = 32 bits
1 frame
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
Lch.DATA
Rch.DATA
Slot No.0
No bit delay
Slot No.1
Setting:
TRMD = 11,
TDLE = 1,
RDLE = 1,
CD0E = 0,
REDG = 1,
TDLA3 to TDLA0 = 0000,
RDLA3 to RDLA0 = 0000,
CD0A3 to CD0A0 = 0000,
FL = 1100 (frame length: 32 bits)
TDRE = 1, TDRA3 to TDRA0 = 0001,
RDRE = 1, RDRA3 to RDRA0 = 0001,
CD1E = 0, CD1A3 to CD1A0 = 0000
Figure 17.16 Transmission and Reception Timings (16-Bit Stereo Data (1))
16-bit Stereo Data (2): L/R method, rising edge sampling, slot No.0 used for left channel transmit
data, slot No.1 used for left channel receive data, slot No.2 used for right channel transmit data,
slot No.3 used for right channel receive data, frame length = 64 bits
Rev. 2.00 Dec. 07, 2005 Page 632 of 950
REJ09B0079-0200