SH7710 Datasheet, PDF (786/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
19.2.9 Receive Missed-Frame Counter Register (RMFCR)
RMFCR is a 16-bit counter that indicates the number of frames missed (discarded, and not
transferred to the receive buffer) during reception. When the receive FIFO overflows, the receive
frames in the FIFO are discarded. The number of frames discarded at this time is counted. When
the value in this register reaches H′FFFF, counting-up is halted. When this register is read, the
counter value is cleared to 0. Write operations to this register have no effect.
Initial
Bit
Bit Name Value R/W Description
31 to 16 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
15 to 0 MFC15 to All 0
R
MFC0
Missed-Frame Counter
Indicate the number of frames that are discarded and
not transferred to the receive buffer during reception.
Rev. 2.00 Dec. 07, 2005 Page 744 of 950
REJ09B0079-0200