SH7710 Datasheet, PDF (116/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
3.2.3 CPU Register Sets
In DSP mode, the status register (SR) in the CPU unit is extended to add control bits and three
control registers: a repeat start register (SR), repeat end register (RE), and module register are
added as control registers.
31 30 29 28 27
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0 MD RB BL
RC[11:0]
0 0 0 DSP DMY DMX M Q I3 I2 I1 I0 RF1 RF0 S
31
RS
0
Repeat Start register (RS)
0
T
Status Register
(SR)
31
RE
0
Repeat End register (RE)
31
16 15
ME
MS
0
MODulo register (MOD)
Figure 3.2 CPU Registers in DSP Mode
Extension of Status Register (SR): In DSP mode, the following control bits are added to the
status register (SR). These added bits are called DSP extension bits. These DSP extension bits are
valid only in DSP mode.
Initial
Bit
Bit Name Value R/W Description
31 to 28 

 For details, refer to section 2, CPU.
27 to 16 RC11 to All 0
RC0
R/W Repeat Counter
Holds the number of repeat times in order to perform loop
control, and can be modified in privileged mode, privileged
DSP mode, or user DSP mode. At reset, this bit is initialized
to 0. This bit is not affected in the exception handling state.
15 to 13 

 For details, refer to section 2, CPU.
12
DSP
0
R/W DSP Bit
Enables or disables the DSP extended functions. If this bit
is set to 1, the DSP extended functions are enabled. This bit
can be modified in privileged mode or privileged DSP mode.
This bit cannot be modified in user DSP mode. At reset, this
bit is initialized to 0. This bit is not affected in the exception
handling state.
Rev. 2.00 Dec. 07, 2005 Page 74 of 950
REJ09B0079-0200