SH7710 Datasheet, PDF (430/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Table 12.11 8-Bit External Device/Little Endian Access and Data Alignment
Data Bus
Strobe Signals
Operation
D31 to D23 to D15 D7 to
D24 D16 to D8 D0
WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0),
DQMUU DQMUL DQMLU DQMLL
Byte access at 0    Data 


Assert
7 to 0
Byte access at 1    Data 


Assert
7 to 0
Byte access at 2    Data 


Assert
7 to 0
Byte access at 3    Data 


Assert
7 to 0
Word
1st time    Data 


Assert
access at 0 at 0
7 to 0
2nd    Data 


Assert
time at
15 to 8
1
Word
1st time    Data 


Assert
access at 2 at 2
7 to 0
2nd    Data 


Assert
time at
15 to 8
3
Longword 1st time    Data 


Assert
access at 0 at 0
7 to 0
2nd    Data 


Assert
time at
15 to 8
1
3rd
   Data 


Assert
time at
23 to
2
16
4th
   Data 


Assert
time at
31 to
3
24
Rev. 2.00 Dec. 07, 2005 Page 388 of 950
REJ09B0079-0200