HD6417705F133V Datasheet, PDF (91/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Addressing
Mode
Instruction
Format Effective Address Calculation Method
Indexed
@(R0, Rn) Effective address is sum of register Rn and R0
register indirect
contents.
Rn
+
Rn + R0
R0
GBR indirect
with
displacement
@(disp:8,
GBR)
Effective address is register GBR contents with
8-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the
operand size.
GBR
disp
+
(Zero-extended)
×
GBR
+ disp × 1/2/4
Calculation
Formula
Rn + R0
Byte: GBR + disp
Word: GBR + disp
×2
Longword: GBR +
disp × 4
Indexed GBR @(R0,
indirect
GBR)
1/2/4
Effective address is sum of register GBR and
R0 contents.
GBR
GBR + R0
+
GBR + R0
R0
PC-relative with @(disp:8,
displacement PC)
Effective address is PC with 8-bit displacement Word: PC + disp × 2
disp added. After disp is zero-extended, it is
Longword:
multiplied by 2 (word) or 4 (longword), according _{PC&H'FFFFFFFC}
to the operand size. With a longword operand, _{+ disp × 4}
the lower 2 bits of PC are masked.
PC
&^*
H'FFFFFFFC
+
disp
(zero-extended)
×
PC + disp × 2
or
PC &
H'FFFFFFFC
+ disp × 4
2/4
*: With longword operand
Rev. 2.00, 09/03, page 43 of 690