HD6417705F133V Datasheet, PDF (218/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Bit Name
6
WM
5 to 0 
Initial
Value R/W
0
R/W
0
R
Description
External Wait Mask Specification
Specify whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
Reserved
These bits are always read as 0. The write value should
always be 0.
CS4WCR
Bit
Bit Name
31 to 18 
17
BW1
16
BW0
15 to 13 
12
SW1
11
SW0
Initial
Value R/W
0
R
0
R/W
0
R/W
0
R
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted between the
second or later access cycles in burst access.
00: 0 cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Delay Cycles from Address, CSn Assertion to RD,
WEn Assertion
Specify the number of delay cycles from address and CSn
assertion to RD and WEn assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 2.00, 09/03, page 170 of 690