HD6417705F133V Datasheet, PDF (489/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

18.3.1 Interrupt Flag Register 0 (IFR0)
IFR0, together with interrupt flag register 1 (IFR1), indicates interrupt status information required
by the application. When an interrupt source is generated, the corresponding bit is set to 1 and an
interrupt request is sent to the CPU according to the combination with interrupt enable register 0
(IER0). Clearing is performed by writing 0 to the bit to be cleared, and 1 to the other bits.
However, EP1FULL and EP2EMPTY are status bits, and cannot be cleared.
Bit Bit Name
Initial
Value R/W Description
7
BRST
0
R/W Bus Reset
This bit is set to 1 when a bus reset signal is detected on
the USB bus.
6
EP1FULL 0
R
EP1 FIFO Full
This bit is set when endpoint 1 receives one packet of
data successfully from the host, and holds a value of 1 as
long as there is valid data in the FIFO buffer.
This is a status bit, and cannot be cleared.
5
EP2TR
0
R/W EP2 Transfer Request
This bit is set if there is no valid transmit data in the FIFO
buffer when an IN token for endpoint 2 is received from
the host. A NACK handshake is returned to the host until
data is written to the FIFO buffer and packet transmission
is enabled.
4
EP2EMPTY 1
R
EP2 FIFO Empty
This bit is set when at least one of the dual endpoint 2
transmit FIFO buffers is ready for transmit data to be
written.
This is a status bit, and cannot be cleared.
3
SETUPTS 0
R/W Setup Command Receive Complete
This bit is set to 1 when endpoint 0 receives successfully
a setup command requiring decoding on the application
side, and returns an ACK handshake to the host.
2
EP0oTS
0
R/W EP0o Receive Complete
This bit is set to 1 when endpoint 0 receives data from the
host successfully, stores the data in the FIFO buffer, and
returns an ACK handshake to the host.
Rev. 2.00, 09/03, page 441 of 690