HD6417705F133V Datasheet, PDF (182/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

6.3.7 Interrupt Request Register 1 (IRR1)
IRR1 is an 8-bit register that indicates whether DMAC or SCIF0 interrupt requests are generated.
Bit
Bit Name
7 TXI0R
6
5 RXI0R
4 ERI0R
3 DEI3R
2 DEI2R
1 DEI1R
Initial
Value R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Description
TXI0 Interrupt Request
Indicates whether a TXI0 (SCIF0) interrupt request is generated.
0: A TXI0 interrupt request is not generated
1: A TXI0 interrupt request is generated
Reserved
This bit is always read as 0.
RXI0 Interrupt Request
Indicates whether an RXI0 (SCIF0) interrupt request is
generated.
0: An RXI0 interrupt request is not generated
1: An RXI0 interrupt request is generated
ERI0 Interrupt Request
Indicates whether an ERI0 (SCIF0) interrupt request is
generated.
0: An ERI0 interrupt request is not generated
1: An ERI0 interrupt request is generated
DEI3 Interrupt Request
Indicates whether a DEI3 (DMAC) interrupt request is generated.
0: A DEI3 interrupt request is not generated
1: A DEI3 interrupt request is generated
DEI2 Interrupt Request
Indicates whether a DEI2 (DMAC) interrupt request is generated.
0: A DEI2 interrupt request is not generated
1: A DEI2 interrupt request is generated
DEI1 Interrupt Request
Indicates whether a DEI1 (DMAC) interrupt request is generated.
0: A DEI1 interrupt request is not generated
1: A DEI1 interrupt request is generated
Rev. 2.00, 09/03, page 134 of 690