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| HD6417705F133V Datasheet, PDF (693/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series | |||
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25.3.5 Burst ROM Timing
CKIO
A25 to A0
BS
CSn
RD/WR
T1
Tw
Twx
T2B
Twb
T2B
tAD1
tAD2
tAD2
tBSD
tBSD
tCSD1
tRWD1
tCSD1
tRWD1
tRSD
RD
D31 to D0
tRDS3
tRDH3
tRSD
tRDS3
tRDH3
WEn
tWED
DACKn
WAIT
tDACD
tWTH
tWTS
tWTH
tWTS
Notes: 1. tRDH3 is specified by earlier one of change of A25 to A0 or the RD rising edge.
2. DACKn is a waveform when active-low is specified.
tWED
tDACD
Figure 25.21 Burst ROM Read Cycle (One Access Wait, One External Wait,
One Burst Wait, Two Bursts)
Rev. 2.00, 09/03, page 645 of 690
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