HD6417705F133V Datasheet, PDF (382/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

14.3.1 Timer Control Registers (TCR)
TCR are 16-bit registers that control the TCNT channels.
TCR register settings should be made only when TCNT operation is stopped.
Initial
Bit
Bit Name Value
15 to 8 
0
7
CCLR2 0
6
CCLR1 0
5
CCLR0 0
4
CKEG1 0
3
CKEG0 0
2
TPSC2 0
1
TPSC1 0
0
TPSC0 0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0 and cannot be modified.
Counter Clear
Select the TCNT clearing source.
000: TCNT clearing disabled
001: TCNT cleared by TGRA compare match
010: TCNT cleared by TGRB compare match
011: Setting prohibited
100: TCNT clearing disabled
101: TCNT cleared by TGRC compare match
110: TCNT cleared by TGRD compare match
111: Setting prohibited
Clock Edge
Select the input clock edge. When the internal clock is
counted using both edges, the input clock period is halved
(e.g. Pφ/4 both edges = Pφ/2 rising edge).
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges^*
[Legend] X: Don’t care
Note: * Internal-clock edge selection is valid when the input
clock is Pφ/4 or slower. If the input clock is Pφ/1, this
operation is not performed.
Timer Prescaler
Select the TCNT count clock. The clock source can be
selected independently for each channel. Table 14.3 shows
the clock sources that can be set for each channel. For more
information on count clock selection, see table 14.4.
Rev. 2.00, 09/03, page 334 of 690