HD6417705F133V Datasheet, PDF (373/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

13.2.2 Compare Match Timer Control/Status Register (CMCSR)
CMCSR is a 16-bit register that indicates the occurrence of compare matches, and sets the
enable/disable of DMA transfer requests and the clock used for incrementation.
Bit
Bit Name Initial Value R/W Description
15 to 8 —
0
R
Reserved
7
CMF
0
These bits are always read as 0. The write value
should always be 0.
R/(W)^* Compare Match Flag
Indicates whether CMCNT and CMCOR values
have matched or not.
0: CMCNT and CMCOR values have not matched
[Clearing condition]
Write 0 to CMF after reading CMF = 1
1: CMCNT and CMCOR values have matched
6, 5
—
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
4
CMR
0
R/W Compare Match Request
0: Disables a DMA transfer request
1: Enables a DMA transfer request
3, 2
—
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1
CKS1
0
R/W Clock Select
0
CKS0
0
R/W Select the clock input to CMCNT from among the
four internal clocks obtained by dividing the
peripheral clock (Pφ). When the STR bit in
CMSTR is set to 1, CMCNT begins incrementing
with the clock selected by the CKS1 and CKS0
bits.
00: P φ/4
01: P φ/8
10: P φ/16
11: P φ/64
Note: *Only 0 can be written for clearing the flags.
Rev. 2.00, 09/03, page 325 of 690