HD6417705F133V Datasheet, PDF (316/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CKIO
Bus cycle
DREQ
(Overrun 0 at high level)
DACK
(Active-high)
CPU
CPU
DMAC
1st acceptance
Non sensitive period
CPU
2nd acceptance
Acceptance
start
CKIO
Bus cycle
DREQ
(Overrun 1 at high level)
DACK
(Active-high)
CPU
CPU
1st acceptance
Non sensitive period
DMAC
CPU
2nd acceptance
Acceptance
start
Figure 8.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
CKIO
Bus cycle
DREQ
(Rising)
DACK
(Active-high)
CPU
CPU
DMAC
Busrst acceptance
Non sensitive period
DMAC
Figure 8.15 Example of DREQ Input Detection in Burst Mode Edge Detection
Rev. 2.00, 09/03, page 268 of 690