HD6417705F133V Datasheet, PDF (355/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

a. Normal operation to hardware standby
CKIO
CA
RESETP
STATUS
Normal^*3
Standby^*2
Undefined
Reset^*1
Normal^*3
2 Rcyc or more^*5
0−10Bcyc^*4
Notes: 1. Reset: HH (STATUS1 high, STATUS0 high)
2. Standby: LH (STATUS1 low, STATUS0 high)
3. Normal: LL (STATUS1 low, STATUS0 low)
4. Bcyc: Bus clock cycle
5. Rcyc: EXTAL2 (32.768 kHz) cycle
0−30Bcyc
Figure 11.10 Hardware Standby Mode
(When CA Goes Low in Normal Operation)
b. Canceling software standby (during WDT operation) to hardware standby
CKIO
CA
RESETP
STATUS
Standby
Normal^*3
Standby^*2
Undefined
Reset^*1
WDT operation
2 Rcyc or more^*5
0−10 Bcyc^*4
Notes: 1. Reset: HH (STATUS1 high, STATUS0 high)
2. Standby: LH (STATUS1 low, STATUS0 high)
3. Normal: LL (STATUS1 low, STATUS0 low)
4. Bcyc: Bus clock cycle
5. Rcyc: EXTAL2 (32.768 kHz) cycle
Figure 11.11 Hardware Standby Mode Timing
(When CA Goes Low during WDT Operation while Standby Mode Is Canceled)
Rev. 2.00, 09/03, page 307 of 690