HD6417705F133V Datasheet, PDF (296/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

8.3.5 DMA Operation Register (DMAOR)
DMAOR is a 16-bit readable/writable register that specifies the priority level of channels at the
DMA transfer. This register shows the DMA transfer status.
Bit
Bit Name
15, 14 
Initial
Value R/W
0
R
13
CMS1 0
R/W
12
CMS0 0
R/W
11, 10 
0
R
9
PR1 0
R/W
8
PR0 0
R/W
7 to 3 
0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Cycle Steal Mode Select
Select either normal mode or intermittent mode in cycle steal
mode.
It is necessary that all channels' bus modes are set to cycle
steal mode to make valid intermittent mode.
00: Normal mode
01: Setting prohibited
10: Intermittent mode 16
Executes one DMA transfer in each of 16 clocks of an
external bus clock.
11: Intermittent mode 64
Executes one DMA transfer in each of 64 clocks of an
external bus clock.
Reserved
These bits are always read as 0. The write value should
always be 0.
Priority Mode
Select the priority level between channels when there are
transfer requests for multiple channels simultaneously.
00: CH0 > CH1 > CH2 > CH3
01: CH0 > CH2 > CH3 > CH1
10: Setting prohibited
11: Round-robin mode
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00, 09/03, page 248 of 690