HD6417705F133V Datasheet, PDF (598/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Bit Name
Initial
Value R/W Description
15 SCMFCA 0
R/W L Bus Cycle Condition Match Flag A
When the L bus cycle condition in the break conditions set
for channel A is satisfied, this flag is set to 1. In order to
clear this flag, write 0 into this bit.
0: The L bus cycle condition for channel A does not match
1: The L bus cycle condition for channel A matches
14 SCMFCB 0
R/W L Bus Cycle Condition Match Flag B
When the L bus cycle condition in the break conditions set
for channel B is satisfied, this flag is set to 1. In order to
clear this flag, write 0 into this bit.
0: The L bus cycle condition for channel B does not match
1: The L bus cycle condition for channel B matches
13 SCMFDA 0
R/W I Bus Cycle Condition Match Flag A
When the I bus cycle condition in the break conditions set for
channel A is satisfied, this flag is set to 1. In order to clear
this flag, write 0 into this bit.
0: The I bus cycle condition for channel A does not match
1: The I bus cycle condition for channel A matches
12 SCMFDB 0
R/W I Bus Cycle Condition Match Flag B
When the I bus cycle condition in the break conditions set for
channel B is satisfied, this flag is set to 1. In order to clear
this flag, write 0 into this bit.
0: The I bus cycle condition for channel B does not match
1: The I bus cycle condition for channel B matches
11 PCTE
0
R/W PC Trace Enable
0: Disables PC trace
1: Enables PC trace
10 PCBA
0
R/W PC Break Select A
Selects the break timing of the instruction fetch cycle for
channel A as before or after instruction execution.
0: PC break of channel A is set before instruction execution
1: PC break of channel A is set after instruction execution
Rev. 2.00, 09/03, page 550 of 690