HD6417705F133V Datasheet, PDF (359/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

12.2 Input/Output Pin
Table 12.1 shows the pin configuration of the TMU.
Table 12.1 Pin Configuration
Name
Clock input
Abbreviation I/O
TCLK
I
Description
External clock input pin/input capture control input pin
12.3 Register Descriptions
The TMU has the following registers. Refer to section 24, List of Registers, for more details of the
addresses of these registers and state of these registers in each processing state. For the register
name for each channel, TCOR for channel 0 is noted as TCOR_0.
1. Common
• Timer start register (TSTR)
2. Channel 0
• Timer constant register_0 (TCOR_0)
• Timer counter_0 (TCNT_0)
• Timer control register_0 (TCR_0)
3. Channel 1
• Timer constant register_1 (TCOR_1)
• Timer counter_1 (TCNT_1)
• Timer control register_1 (TCR_1)
4. Channel 2
• Timer constant register_2 (TCOR_2)
• Timer counter_2 (TCNT_2)
• Timer control register_2 (TCR_2)
• Input capture register_2 (TCPR_2)
Rev. 2.00, 09/03, page 311 of 690