HD6417705F133V Datasheet, PDF (438/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

16.3.8 Serial Status Register (SCSSR)
SCSSR is a 16-bit readable/writable register that indicates the SCIF status.
However, 1 cannot be written to the ORER, TSF, ER, TDFE, BRK, RDF, and DR flags. Also note
that in order to clear these flags to 0, they must be read as 1 beforehand. The TEND, FER, and
PER flags are read-only flags and cannot be modified.
Bit
15 to 10
Bit
Name

Initial
Value
0
9
ORER 0
R/W
R
R/(W)^*
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Overrun Error
Indicates that an overrun error occurred during
reception.
This bit is only valid in asynchronous mode.
0: Reception in progress, or reception has ended
successfully^*1
[Clearing conditions]
• Power-on reset or manual reset
• When 0 is written to ORER after reading ORER =
1
1: An overrun error occurred during reception^*2
[Setting condition]
When serial reception is completed while receive
FIFO is full
Notes: 1. The ORER flag is not affected and retains
its previous state when the RE bit in
SCSCR is cleared to 0.
2. The receive data prior to the overrun error
is retained in SCFRDR, and the data
received subsequently is lost. Serial
reception cannot be continued while the
ORER flag is set to 1.
Rev. 2.00, 09/03, page 390 of 690