HD6417705F133V Datasheet, PDF (22/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

3.3.2 TLB Indexing.................................................................................................. 77
3.3.3 TLB Address Comparison ............................................................................... 78
3.3.4 Page Management Information ........................................................................ 80
3.4 MMU Functions .......................................................................................................... 81
3.4.1 MMU Hardware Management ......................................................................... 81
3.4.2 MMU Software Management .......................................................................... 81
3.4.3 MMU Instruction (LDTLB)............................................................................. 82
3.4.4 Avoiding Synonym Problems .......................................................................... 83
3.5 MMU Exceptions ........................................................................................................ 85
3.5.1 TLB Miss Exception ....................................................................................... 85
3.5.2 TLB Protection Violation Exception ................................................................ 86
3.5.3 TLB Invalid Exception .................................................................................... 87
3.5.4 Initial Page Write Exception ............................................................................ 88
3.6 Memory-Mapped TLB................................................................................................. 90
3.6.1 Address Array ................................................................................................. 90
3.6.2 Data Array ...................................................................................................... 90
3.6.3 Usage Examples.............................................................................................. 92
3.7 Usage Note .................................................................................................................. 92
Section 4 Cache..............................................................................................93
4.1 Features....................................................................................................................... 93
4.1.1 Cache Structure............................................................................................... 93
4.2 Register Descriptions................................................................................................... 95
4.2.1 Cache Control Register 1 (CCR1).................................................................... 96
4.2.2 Cache Control Register 2 (CCR2).................................................................... 97
4.2.3 Cache Control Register 3 (CCR3).................................................................... 100
4.3 Operation .................................................................................................................... 101
4.3.1 Searching the Cache ........................................................................................ 101
4.3.2 Read Access.................................................................................................... 102
4.3.3 Prefetch Operation .......................................................................................... 102
4.3.4 Write Access ................................................................................................... 102
4.3.5 Write-Back Buffer........................................................................................... 103
4.3.6 Coherency of Cache and External Memory ...................................................... 103
4.4 Memory-Mapped Cache............................................................................................... 104
4.4.1 Address Array ................................................................................................. 104
4.4.2 Data Array ...................................................................................................... 105
4.4.3 Usage Examples.............................................................................................. 107
4.5 Usage Note .................................................................................................................. 108
Section 5 Exception Handling ........................................................................109
5.1 Register Descriptions................................................................................................... 109
5.1.1 TRAPA Exception Register (TRA).................................................................. 110
5.1.2 Exception Event Register (EXPEVT) .............................................................. 111
Rev. 2.00, 09/03, page xx of xlvi