HD6417705F133V Datasheet, PDF (18/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Item
25.3.1 Clock Timing
Figure 25.5 Power-On
Oscillation Settling Time
25.3.2 Control Signal
Timing
Table 25.6 Control Signal
Timing
Figure 25.15 Pin Drive
Timing at Standby
Page
633
636
638
Revisions (See Manual for Details)
Figure amended
CKIO,
internal clock
Stable oscillation
V_CC
RESETP
TRST
V_CC min
t_OSC1
t_RESPW
t_RESPS
Conditions amended
(Conditions: VCCQ = VCC-RTC = VCC-USB = 3.0 to 3.6 V,
VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to 1.6 V, AVCC = 3.0 to
3.6 V, VSSQ = VSS = VSS-RTC = VSS-USB = VSS-PLL1 = VSS-
PLL2 = AVSS = 0 V, Ta = –20 to 75°C, Clock mode
0/1/2/4/5/6/7)
Note *1 amended
Note: 1. RESETP, RESETM, NMI, and IRQ5 to IRQ0 are
asynchronous. ⋅⋅⋅⋅⋅⋅
Figure amended
Normal mode
Standby mode
Normal mode
CKIO
t_STD
STATUS 0
STATUS 1
25.3.4 Basic Timing
Figure 25.16 Basic Bus
Cycle (No Wait)
640
Note *2 added
t_WED
WEn ^*2
Write
t_WDD1
D31 to D0
t_WED
t_AH
t_WDH1
t_WDH4
Figure 25.17 Basic Bus 641
Cycle (One Software Wait)
Notes: 1. DACKn is a waveform when active-low is specified.
2. Output timing is the same when reading byte-selection SRAM.
Note *2 added
WEn ^*2
Write
D31 to D0
t_WED
t_WDD1
t_WED
t_AH
t_WDH1
t_WDH4
Notes: 1. DACKn is a waveform when active-low is specified.
2. Output timing is the same when reading byte-selection SRAM.
Rev. 2.00, 09/03, page xvi of xlvi