HD6417705F133V Datasheet, PDF (440/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit Name Value R/W
Description
6 TEND 1
R
Transmit End
Indicates that there is no valid data in SCFTDR when the
last bit of the transmit character is sent, and transmission
has been ended.
0: Transmission is in progress
[Clearing condition]
When data is written to SCFTDR
1: Transmission has been ended
[Setting condition]
5 TDFE 1
R/(W)^*
When there is no transmit data in SCFTDR on transmission
of a 1-byte serial transmit character
Transmit FIFO Data Empty
Indicates that data has been transferred from SCFTDR to
SCTSR, the number of data bytes in SCFTDR has fallen to
or below the transmit trigger data number set by bits
TTRG1 and TTRG0 in the FIFO control register (SCFCR),
and new transmit data can be written to SCFTDR.
0: A number of transmit data bytes exceeding the transmit
trigger set number have been written to SCFTDR
[Clearing condition]
When transmit data exceeding the transmit trigger set
number is written to SCFTDR, and 0 is written to TDFE
after reading TDFE = 1
1: The number of transmit data bytes in SCFTDR does not
exceed the transmit trigger set number
[Setting conditions]
• Power-on reset or manual reset
• When the number of SCFTDR transmit data bytes falls
to or below the transmit trigger set number as the result
of a transmit operation^*1
Note: 1. As SCFTDR is a 64-byte FIFO register, the
maximum number of bytes that can be written
when TDFE = 1 is 64 – (transmit trigger set
number). Data written in excess of this will be
ignored. The number of data bytes in SCFTDR is
indicated by SCFDR.
Rev. 2.00, 09/03, page 392 of 690