HD6417705F133V Datasheet, PDF (597/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

22.2.9 Break Control Register (BRCR)
BRCR sets the following conditions:
1. Specifies whether channels A and B are used in two independent channel conditions or under
the sequential condition.
2. Specifies whether a break is set before or after instruction execution.
3. Specifies whether to include the number of execution times on channel B in comparison
conditions.
4. Specifies whether to include data bus on channel B in comparison conditions.
5. Enables PC trace.
6. Enables ASID check.
BRCR is a 32-bit readable/writable register that has break conditions match flags and bits for
setting a variety of break conditions.
Bit
31 to 22
Bit
Name

21
BASMA
20
BASMB
19 to 16 
Initial
Value
0
0
0
0
R/W
R
R/W
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Break ASID Mask A
Specifies whether bits in channel A break ASID7 to
ASID0 (BASA7 to BASA0) which are set in BASRA are
masked or not.
0: All BASRA bits are included in the break conditions
and the ASID is checked
1: All BASRA bits are not included in the break conditions
and the ASID is not checked
Break ASID Mask B
Specifies whether bits in channel B break ASID7 to
ASID0 (BASB7 to BASB0) which are set in BASRB are
masked or not.
0: All BASRB bits are included in the break conditions
and the ASID is checked
1: All BASRB bits are not included in the break conditions
and the ASID is not checked
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00, 09/03, page 549 of 690