HD6417705F133V Datasheet, PDF (102/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Table 2.7 Arithmetic Operation Instructions
Instruction
ADD
Rm,Rn
ADD
#imm,Rn
ADDC
Rm,Rn
ADDV
Rm,Rn
CMP/EQ #imm,R0
CMP/EQ Rm,Rn
CMP/HS Rm,Rn
CMP/GE Rm,Rn
CMP/HI Rm,Rn
CMP/GT Rm,Rn
CMP/PL Rn
CMP/PZ Rn
CMP/STR Rm,Rn
DIV1
Rm,Rn
DIV0S
Rm,Rn
DIV0U
DMULS.L Rm,Rn
DMULU.L Rm,Rn
DT
Rn
Instruction Code Operation
Privileged
Mode
Cycles T Bit
0011nnnnmmmm1100 Rn+Rm→Rn
–
1
–
0111nnnniiiiiiii
Rn+imm→Rn
–
1
–
0011nnnnmmmm1110 Rn+Rm+T→Rn, Carry→T
–
1
Carry
0011nnnnmmmm1111 Rn+Rm→Rn, Overflow→T
–
1
Overflow
10001000iiiiiiii
If R0 = imm, 1 → T
–
1
Comparison
result
0011nnnnmmmm0000 If Rn = Rm, 1 → T
–
1
Comparison
result
0011nnnnmmmm0010 If Rn ≥ Rm with unsigned data, 1 –
→T
1
Comparison
result
0011nnnnmmmm0011 If Rn ≥ Rm with signed data, 1 → –
T
1
Comparison
result
0011nnnnmmmm0110 If Rn > Rm with unsigned data, 1 –
→T
1
Comparison
result
0011nnnnmmmm0111 If Rn > Rm with signed data, 1 → –
T
1
Comparison
result
0100nnnn00010101 If Rn ≥ 0, 1 → T
–
1
Comparison
result
0100nnnn00010001 If Rn > 0, 1 → T
–
1
Comparison
result
0010nnnnmmmm1100 If Rn and Rm have an equivalent –
byte, 1 → T
1
Comparison
result
0011nnnnmmmm0100 Single-step division (Rn/Rm) –
1
Calculation
result
0010nnnnmmmm0111 MSB of Rn → Q, MSB of Rm → –
M, M ^ Q → T
1
Calculation
result
0000000000011001 0 → M/Q/T
–
1
0
0011nnnnmmmm1101 Signed operation of Rn × Rm → –
MACH, MACL 32 × 32 → 64 bits
2 (to –
5)^*
0011nnnnmmmm0101 Unsigned operation of Rn × Rm –
→ MACH, MACL 32 × 32 → 64
bits
2 (to –
5)^*
0100nnnn00010000
Rn – 1 → Rn, if Rn = 0, 1 → T, –
else 0 → T
1
Comparison
result
Rev. 2.00, 09/03, page 54 of 690