HD6417705F133V Datasheet, PDF (183/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit Name Value R/W Description
0 DEI0R 0
R
DEI0 Interrupt Request
Indicates whether a DEI0 (DMAC) interrupt request is generated.
0: A DEI0 interrupt request is not generated
1: A DEI0 interrupt request is generated
6.3.8 Interrupt Request Register 2 (IRR2)
IRR2 is an 8-bit register that indicates whether SCIF2 or ADC interrupt requests are generated.
Bit
Bit Name
7 to 5 
Initial
Value R/W
0
R
4 ADIR 0
R
3 TXI2R 0
R
2

0
R
1 RXI2R 0
R
0 ERI2R 0
R
Description
Reserved
These bits are always read as 0.
ADI Interrupt Request
Indicates whether an ADI (ADC) interrupt request is generated.
0: An ADI interrupt request is not generated
1: An ADI interrupt request is generated
TXI2 Interrupt Request
Indicates whether a TXI2 (SCIF2) interrupt request is generated.
0: A TXI2 interrupt request is not generated
1: A TXI2 interrupt request is generated
Reserved
This bit is always read as 0.
RXI2 Interrupt Request
Indicates whether an RXI2 (SCIF2) interrupt request is
generated.
0: An RXI2 interrupt request is not generated
1: An RXI2 interrupt request is generated
ERI2 Interrupt Request
Indicates whether an ERI2 (SCIF2) interrupt request is
generated.
0: An ERI2 interrupt request is not generated
1: An ERI2 interrupt request is generated
Rev. 2.00, 09/03, page 135 of 690