HD6417705F133V Datasheet, PDF (434/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit
Name Value R/W Description
9
BRIE 0
R/W Break Interrupt Enable
Enables or disables generation of a break-receive
interrupt when the BRK flag in SCSSR is set to 1.
0: Break-receive interrupt disabled^*
1: Break-receive interrupt enabled
Note: * The interrupt request is cleared by clearing the
BRK flag to 0 after reading 1 from it or clearing
the BRIE bit to 0.
8
DRIE 0
R/W Receive Data Ready Interrupt Enable
Enables or disables generation of a receive-data-ready
interrupt when the DR flag in SCSSR is set to 1.
0: Receive-data-ready interrupt disabled^*
1: Receive-data-ready interrupt enabled
Note: * The interrupt request is cleared by clearing the
DR flag to 0 after reading 1 from it or clearing the
DRIE bit to 0.
7
TIE
0
R/W Transmit Interrupt Enable
Enables or disables generation of a transmit-FIFO-data-
empty interrupt request when the TDFE flag in SCSSR is
set to 1.
0: Transmit-FIFO-data-empty interrupt request
disabled^*
1: Transmit-FIFO-data-empty interrupt request enabled
Note: * The interrupt request is cleared by writing
transmit data exceeding the transmit trigger set
number to SCFTDR, reading 1 from the TDFE
flag, then clearing it to 0, or clearing the TIE bit to
0.
6
RIE
0
R/W Receive Interrupt Enable
Enables or disables generation of a receive-FIFO-data-
full interrupt request when the RDF flag in SCSSR is set
to 1.
0: Receive-FIFO-data-full interrupt request disabled^*
1: Receive-FIFO-data-full interrupt request enabled
Note: * The interrupt requests is cleared by reading 1
from the RDF flag, then clearing the flag to 0, or
clearing the RIE bit to 0.
Rev. 2.00, 09/03, page 386 of 690