HD6417705F133V Datasheet, PDF (571/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

PMCR State
PM4MD1 PM4MD0 Pin State
0
0
NF
1
Setting
Prohibited
1
0
Input (Pull-up
MOS on)
1
Input (Pull-up
MOS off)
Read
Write
PMDR value Data can be written to PMDR but no effect
on pin state.
PMDR value Written data is output from the pin.
Pin state
Pin state
Data can be written to PMDR but no effect
on pin state.
Data can be written to PMDR but no effect
on pin state.
20.13 Port N
Port N is an 8-bit input/output port with the pin configuration shown in figure 20.13. Each pin has
an input pull-up MOS, which is controlled by the port N control register (PNCR) in the PFC.
Port N
PTN7 (input/output)
PTN6 (input/output)/DPLS (input)
PTN5 (input/output)/DMNS (input)
PTN4 (input/output)/TXDPLS (output)
PTN3 (input/output)/TXDMNS (output)
PTN2 (input/output)/XVDATA (input)
PTN1 (input/output)/TXENL (output)
PTN0 (input/output)/SUSPND (output)
Figure 20.13 Port N
20.13.1 Register Description
Port N has the following register. For details on the register address and access size, see section
24, List of Registers.
• Port N data register (PNDR)
20.13.2 Port N Data Register (PNDR)
PNDR is an 8-bit readable/writable register that stores data for pins PTN7 to PTN0. Bits PN7DT
to PN0DT correspond to pins PTN7 to PTN0. When the pin function is general output port, if the
port is read, the value of the corresponding PNDR bit is returned directly. When the function is
general input port, if the port is read, the corresponding pin level is read.
Rev. 2.00, 09/03, page 523 of 690