HD6417705F133V Datasheet, PDF (16/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Item
9.1 Features
Figure 9.1 Block Diagram
of Clock Pulse Generator
Page
272
Revisions (See Manual for Details)
Figure amended
Bus interface
10.2.2 Watchdog Timer 289
Control/Status Register
(WTCSR)
11.6.1 Transition to
301
Module Standby Function
16.5 SCIF Interrupt
427
Sources and DMAC
Table 16.4 SCIF Interrupt
Sources
Peripheral bus
Note added
Note: If manual reset is selected using the RSTS bit, a
frequency division ratio of 1/16, 1/32, 1/64, 1/256, 1/1,024,
or 1/4,096 is selected using bits CKS2 to CKS0, and a
watchdog timer counter overflow occurs, resulting in a
manual reset, the LSI will generate two manual resets in
succession. This will not affect its operation but will cause
change in the state of the STATUS pin.
Description amended
This function can be used to reduce the power consumption
in the normal mode and sleep mode.
Table amended
Interrupt
Source
Description
DMAC Activation
ERI
Interrupt initiated by receive error flag Not possible
(ER) or break flag (BRK)
RXI
Interrupt initiated by receive FIFO data Possible^*1
full flag (RDF) or receive data ready
(DR)
TXI
Interrupt initiated by transmit FIFO data Possible^*2
empty flag (TDFE) or transmit data stop
flag (TSF)
18.1 Features
19.2.7 Port F Control
Register (PFCR)
19.2.9 Port G Control
Register (PGCR)
437 Description amended
• The UDC (USB device controller) conforming to USB2.0
and transceiver process USB protocol automatically.
489 Note *2 added to Bits 15 and 14
Note 2. Pull-up MOS on.
491 Note *2 added to Bits 7 to 0
Note 2. Pull-up MOS on.
Rev. 2.00, 09/03, page xiv of xlvi