HD6417705F133V Datasheet, PDF (447/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Bit Name
7 RTRG1
6 RTRG0
5 TTRG1
4 TTRG0
3 MCE
Initial
Value R/W Description
0
R/W Receive FIFO Data Number Trigger
0
R/W _{Set the number of receive data bytes that sets the receive}
data full (RDF) flag in the serial status register (SCSSR).
The RDF flag is set when the number of receive data bytes
in SCFRDR is equal to or greater than the trigger set
number shown in below.
00: 1
01: 16
10: 32
11: 48
0
R/W Transmit FIFO Data Number Trigger
0
R/W _{Set the number of remaining transmit data bytes that sets}
the transmit FIFO data register empty (TDFE) flag in the
serial status register (SCSSR).
The TDFE flag is set when, as the result of a transmit
operation, the number of transmit data bytes in the transmit
FIFO data register (SCFTDR) falls to or below the trigger
set number shown in below.
00: 32 (32)
01: 16 (48)
10: 2 (62)
11: 0 (64)
Note: The values in parentheses are the number of empty
bytes in SCFTDR when the flag is set.
0
R/W Modem Control Enable
Enables modem control signals CTS and RTS.
This setting is only valid in asynchronous mode.
0: Modem signal disabled^*
1: Modem signal enabled
Note: * CTS is fixed at active 0 regardless of the input
value, and RTS is also fixed at 0.
Rev. 2.00, 09/03, page 399 of 690