HD6417705F133V Datasheet, PDF (217/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

2. Burst ROM
CS0WCR
Bit
Bit Name
31 to 18 
17
BW1
16
BW0
15 to 11 
10
W3
9
W2
8
W1
7
W0
Initial
Value R/W
0
R
0
R/W
0
R/W
0
R
1
R/W
0
R/W
1
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted between the
second or later access cycles in burst access.
00: 0 cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Access Wait Cycles
Specify the number of wait cycles to be inserted in the first
read/write access cycle.
0000: 0 cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Setting prohibited
1110: Setting prohibited
1111: Setting prohibited
Rev. 2.00, 09/03, page 169 of 690