HD6417705F133V Datasheet, PDF (224/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit Name Value R/W
11
RFSH 0
R/W
10
RMODE 0
R/W
9

0
R
8
BACTV 0
R/W
7 to 5 
0
R
4
A3ROW1 0
R/W
3
A3ROW0 0
R/W
Description
Refresh Control
Specifies whether or not the refresh operation of the SDRAM
is performed.
0: No refresh
1: Refresh
Refresh Control
Specifies whether to perform auto-refresh or self-refresh
when the RFSH bit is 1. When the RFSH bit is 1 and this bit is
1, self-refresh starts immediately. When the RFSH bit is 1 and
this bit is 0, auto-refresh starts according to the contents that
are set in registers RTCSR, RTCNT, and RTCOR.
0: Auto-refresh is performed
1: Self-refresh is performed
Reserved
This bit is always read as 0. The write value should always be
0.
Bank Active Mode
Specifies to access whether in auto-precharge mode (using
READA and WRITA commands) or in bank active mode
(using READ and WRIT commands).
0: Auto-precharge mode (using READA and WRITA
commands)
1: Bank active mode (using READ and WRIT commands)
Note:
Bank active mode can be used only when either the
upper or lower bits of the CS3 space are used. When
both the CS2 and CS3 spaces are set to SDRAM,
specify the auto-precharge mode.
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Bits of Row Address for Area 3
Specifies the number of bits of the row address for area 3.
00: 11 bits
01: 12 bits
10: 13 bits
11: Setting prohibited
Rev. 2.00, 09/03, page 176 of 690