HD6417705F133V Datasheet, PDF (304/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

On-Chip Peripheral Module Request Mode: In this mode a transfer is performed at the transfer
request signal of an on-chip peripheral module. Transfer request signals comprise the transmit data
empty transfer request and receive data full transfer request from the SCIF0 and SCIF2 set by
DMARS0/1, the compare-match timer transfer request from the CMT, and transfer requests from
the USB.
When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0,
NMIF = 0), a transfer is performed upon the input of a transfer request signal.
When a transmit data empty transfer request of the SCIF is set as the transfer request, the transfer
destination must be the SCIF’s transmit data register. Likewise, when receive data full transfer
request of the SCIF is set as the transfer request, the transfer source must be the SCIF’s receive
data register. These conditions also apply to the USB. Any address can be specified for data source
and destination, when transfer request is generated by the CMT.
Table 8.6 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits
DMA Transfer
Request
DMA Transfer
RS3 RS2 RS1 RS0 Source
Request Signal
1 1 1 0 ADC
AD-conversion end request
Source
ADDR
1 1 1 1 CMT
Compare-match transfer
Any
request
Destination
Any
Any
Bus
Mode
Cycle
steal
Burst/
cycle
steal
Table 8.7 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits
CHCR
RS[3:0]
1000
DMARS
DMA Transfer
Request
DMA Transfer
MID
RID Source
Request Signal
001000 01 SCIF0
transmitter
TXI0
(transmit FIFO data empty)
10 SCIF0
receiver
RXI0
(receive FIFO data full)
001010 01 SCIF2
transmitter
TXI2
(transmit FIFO data empty)
10 SCIF2
receiver
RXI2
(receive FIFO data full)
011100 11 USB
transmitter
EP2 FIFO empty transfer
request
00 USB
receiver
EP1 FIFO full transfer
request
Source
Any
SCFRDR_0
Any
SCFRDR_2
Any
EPDR1
Destination
SCFTDR_0
Any
SCFTDR_2
Any
EPDR2
Any
Bus
Mode
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Rev. 2.00, 09/03, page 256 of 690