HD6417705F133V Datasheet, PDF (380/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

14.2 Input/Output Pins
Table 14.2 shows the pin configuration of the TPU.
Table 14.2 Pin Configuration
Channel
0
1
2
3
Name
Output compare
match 0
Output compare
match 1
Output compare
match 2
Output compare
match 3
Symbol I/O
TO0
O
TO1
O
TO2
O
TO3
O
Function
TGR0A output compare output/PWM output
pin
TGR1A output compare output/PWM output
pin
TGR2A output compare output/PWM output
pin
TGR3A output compare output/PWM output
pin
14.3 Register Descriptions
The TPU has the following registers. Refer to section 24, List of Registers, for more details of the
addresses of these registers and state of these registers in each processing state. For the register
name for each channel, TCR for channel 0 is noted as TCR_0.
1. Channel 0
• Timer control register_0 (TCR_0)
• Timer mode register_0 (TMDR_0)
• Timer I/O control register_0 (TIOR_0)
• Timer interrupt enable register_0 (TIER_0)
• Timer status register_0 (TSR_0)
• Timer counter_0 (TCNT_0)
• Timer general register A_0 (TGRA_0)
• Timer general register B_0 (TGRB_0)
• Timer general register C_0 (TGRC_0)
• Timer general register D_0 (TGRD_0)
2. Channel 1
• Timer control register_1 (TCR_1)
• Timer mode register_1 (TMDR_1)
• Timer I/O control register_1 (TIOR_1)
• Timer interrupt enable register_1 (TIER_1)
• Timer status register_1 (TSR_1)
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