HD6417705F133V Datasheet, PDF (504/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

1. Setup Stage
USB function
SETUP token reception
Receive 8-byte command
data in EP0s
Application
Command
to be processed by
application?
No
Automatic
processing by
this module
Yes
Set setup command
reception complete flag
(IFR0.SETUP TS = 1)
Interrupt request
Clear SETUP TS flag
(IFR0.SETUP TS = 0)
Clear EP0i FIFO (CLR.EP0iCLR = 1)
Clear EP0o FIFO (CLR.EP0oCLR = 1)
To data stage
Read 8-byte data from EP0s
Decode command data
Determine data stage direction^*1
Write 1 to EP0s read complete bit
(TRG.EP0s RDFN = 1)
To control-in
data stage
*2
To control-out
data stage
Notes: 1. In the setup stage, the application analyzes command data from the host requiring processing by
the application, and determines the subsequent processing (for example, data stage direction, etc.).
2. When the transfer direction is control-out, the EP0i transfer request interrupt required in the status
stage should be enabled here. When the transfer direction is control-in, this interrupt is not required
and should be disabled.
Figure 18.5 Setup Stage Operation
Rev. 2.00, 09/03, page 456 of 690