HD6417705F133V Datasheet, PDF (276/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

7.8.9 Low-Frequency Mode
When the SLOW bit in SDCR is set to 1, output of commands, addresses, and write data, and
fetch of read data are performed at a timing suitable for operating SDRAM at a low frequency.
Figure 7.28 shows the access timing in low-frequency mode. In this mode, commands, addresses,
and write data are output in synchronization with the falling edge of CKIO, which is half a cycle
delayed than the normal timing. Read data is fetched at the rising edge of CKIO, which is half a
cycle faster than the normal timing. This timing allows the hold time of commands, addresses,
write data, and read data to be extended.
If SDRAM is operated at a high frequency with the SLOW bit set to 1, the setup time of
commands, addresses, write data, and read data are not guaranteed. Take the operating frequency
and timing design into consideration when making the SLOW bit setting.
CKIO
CKE
A25 to A0
A12/A11^*1
CSn
RASU/L
CASU/L
RD/WR
DQMxx^*2
D31 to D0
BS
DACKn^*3
Tr
Tc1
Tw
Td1
Tde
Tap
Tr
Tc1 Tnop
Trwl
Tap
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. xx is UU, UL, LU, or LL.
3. The waveform for DACKn is when active low is specified.
Figure 7.28 Low-Frequency Mode Access Timing
Rev. 2.00, 09/03, page 228 of 690