HD6417705F133V Datasheet, PDF (684/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

25.3.2 Control Signal Timing
Table 25.6 Control Signal Timing
(Conditions: VCCQ = VCC-RTC = VCC-USB = 3.0 to 3.6 V, VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to
1.6 V, AVCC = 3.0 to 3.6 V, VSSQ = VSS = VSS-RTC = VSS-USB = VSS-PLL1 = VSS-PLL2 =
AVSS = 0 V, Ta = –20 to 75°C, Clock mode 0/1/2/4/5/6/7)
66.67 MHz^*2
Item
RESETP pulse width
RESETP setup time^*1
RESETM pulse width
RESETM setup time
BREQ setup time
BREQ hold time
NMI setup time^*1
NMI hold time
IRQ5 to IRQ0 setup time^*1
Symbol
tRESPW
tRESPS
tRESMW
tRESMS
tBREQS
tBREQH
tNMIS
tNMIH
tIRQS
Min
20^*3
Max
—
20
—
20^*4
—
10
—
1/2 tcyc+10 —
1/2 tcyc+3 —
10
—
3
—
10
—
Unit
tcyc
ns
tcyc
ns
ns
ns
ns
ns
ns
Figure
25.12
25.14
25.13
IRQ5 to IRQ0 hold time
BACK delay time
tIRQH
3
tBACKD
—
—
ns
1/2 tcyc+13 ns
25.14
STATUS1, STATUS0 delay time
tSTD
—
18
ns
25.15
Bus tri-state delay time 1
tBOFF1
0
30
ns
25.14,
Bus tri-state delay time 2
Bus buffer-on time 1
tBOFF2
0
tBON1
0
30
ns
25.15
30
ns
Bus buffer-on time 2
tBON2
0
30
ns
Notes: tcyc is the external bus clock cycle (B clock cycle).
1. RESETP, RESETM, NMI, and IRQ5 to IRQ0 are asynchronous. Changes are detected
at the clock rise when the setup shown is kept. When the setup cannot be kept,
detection can be delayed until the next clock rises.
2. The upper limit of the external bus clock is 66.67 MHz.
3. In standby mode, tRESPW = tOSC2 (10 ms). When the crystal oscillation continues or the
clock multiplication ratio is changed in standby mode, tRESPW = tPLL1 (100 µs).
4. In standby mode, tRESMW = tOSC2 (10 ms). When the crystal oscillation continues or the
clock multiplication ratio is changed in standby mode, RESETM must be kept low until
STATUS (0-1) changes to reset (HH).
Rev. 2.00, 09/03, page 636 of 690