HD6417705F133V Datasheet, PDF (511/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

data transmission is completed, the FIFO used in the data transmission becomes empty. If the
other FIFO contains valid transmit data at this time, transmission can be continued.
When transmission of all data has been completed, write 0 to the EP2EMPTY bit in IER0 and
disable interrupt requests.
18.4.6 EP3 Interrupt-In Transfer
USB function
Application
IN token reception
Valid data
in EP3FIFO?
Yes
No
NACK
Data transmission to host
ACK
Is there data
No
for transmission
to host?
Yes
Write data to EP3 data
register (EPDR3)
Write 1 to EP3 packet
enable bit
(TRG.EP3 PKTE = 1)
Set EP3 transmission
complete flag
(IFR1.EP3 TS = 1)
Interrupt request
Clear EP3 transmission
complete flag
(IFR1.EP3 TS = 0)
Is there data
No
for transmission
to host?
Yes
Write data to EP3 data
register (EPDR3)
Write 1 to EP3 packet
enable bit
(TRG.EP3 PKTE = 1)
Note: This flowchart shows just one example of interrupt transfer processing. Other possibilities include an
operation flow in which, if there is data to be transferred, the EP3 DE bit in the data status register is
referenced to confirm that the FIFO is empty, and then data is written to the FIFO.
Figure 18.12 Operation of EP3 Interrupt-In Transfer
Rev. 2.00, 09/03, page 463 of 690