HD6417705F133V Datasheet, PDF (492/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

18.3.5 Interrupt Enable Register 0 (IER0)
IER0 enables the interrupt requests of interrupt flag register 0 (IFR0). When an interrupt flag is set
to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the
CPU. The interrupt vector number is determined by the contents of interrupt select register 0
(ISR0).
Bit Bit Name
Initial Value R/W
7
BRST
0
R/W
6
EP1FULL
0
R/W
5
EP2TR
0
R/W
4
EP2EMPTY 1
R/W
3
SETUPTS 0
R/W
2
EP0oTS
0
R/W
1
EP0iTR
0
R/W
0
EP0iTS
0
R/W
Description
Bus Reset
EP1 FIFO Full
EP2 Transfer Request
EP2 FIFO Empty
Setup Command Receive Complete
EP0o Receive Complete
EP0i Transfer Request
EP0i Transmit Complete
18.3.6 Interrupt Enable Register 1 (IER1)
IER1 enables the interrupt requests of interrupt flag register 1 (IFR1). When an interrupt flag is set
to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the
CPU. The interrupt vector number is determined by the contents of interrupt select register 1
(ISR1).
Bit Bit Name Initial Value R/W
7 to 3 
0
R
2
EP3TR
0
R/W
1
EP3TS
0
R/W
0
VBUS
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
EP3 Transfer Request
EP3 Transmit Complete
USB Bus Connect
Rev. 2.00, 09/03, page 444 of 690