HD6417705F133V Datasheet, PDF (683/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Stable input clock
EXTAL input
or CKIO input
PLL synchronization
PLL output,
CKIO output
Internal clock
PINT15 to PINT0,
IRQ5 to IRQ0/IRL3 to IRL0 interrupt request
Stable input clock
t_IRLSTB
t_PLL1
PLL synchronization
STATUS 0
STATUS 1
Normal
Standby
Normal
Note: PLL oscillation settling time when clock is input from
EXTAL pin or CKIO pin in oscillation continuous mode.
Figure 25.10 PLL Synchronization Settling Time by IRQ/IRL, PINT Interrupts
Multiplication ratio modified
EXTAL input^*1
(CKIO input)
CKIO output^*2
(PLL output)
Internal clock
t_PLL2
Notes: 1. CKIO input in clock mode 7
2. PLL output except in clock mode 7
Figure 25.11 PLL Synchronization Settling Time when Frequency Multiplication
Ratio Modified
Rev. 2.00, 09/03, page 635 of 690