HD6417705F133V Datasheet, PDF (326/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Clock
Mode _FRQCR*¹ PLL1
PLL2
Input Clock / Crystal
Clock Rate^{*2 Resonator Frequency}
(I:B:P)
Range
CKIO Frequency Range
7
H'1000 ON (× 1) OFF
1:1:1
20.00 MHz to 33.34 MHz 20.00 MHz to 33.34 MHz
H'1001 ON (× 1) OFF
1:1:1/2
20.00 MHz to 66.67 MHz 20.00 MHz to 66.67 MHz
H'1003 ON (× 1) OFF
1:1:1/4
20.00 MHz to 66.67 MHz 20.00 MHz to 66.67 MHz
H'1101 ON (× 2) OFF
2:1:1
20.00 MHz to 33.34 MHz 20.00 MHz to 33.34 MHz
H'1103 ON (× 2) OFF
2:1:1/2
20.00 MHz to 66.67 MHz 20.00 MHz to 66.67 MHz
H'1111 ON (× 2) OFF
1:1:1
20.00 MHz to 33.34 MHz 20.00 MHz to 33.34 MHz
H'1113 ON (× 2) OFF
1:1:1/2
20.00 MHz to 66.67 MHz 20.00 MHz to 66.67 MHz
H'1202 ON (× 3) OFF
3:1:1
26.70 MHz to 33.34 MHz 26.70 MHz to 33.34 MHz
H'1222 ON (× 3) OFF
1:1:1
26.70 MHz to 33.34 MHz 26.70 MHz to 33.34 MHz
H'1303 ON (× 4) OFF
4:1:1
20.00 MHz to 33.34 MHz 20.00 MHz to 33.34 MHz
H'1313 ON (× 4) OFF
2:1:1
20.00 MHz to 33.34 MHz 20.00 MHz to 33.34 MHz
H'1333 ON (× 4) OFF
1:1:1
20.00 MHz to 33.34 MHz 20.00 MHz to 33.34 MHz
Notes: 1. This LSI cannot operate in an FRQCR value other than that listed in table 9.3.
2. Taking input clock frequency ratio as 1.
Cautions:
1. The input to divider 1 is the output of the PLL circuit 1.
2. The frequency of the internal clock (Iφ) is:
• The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL
circuit 1, and the division ratio of divider 1.
• Do not set the internal clock frequency lower than the CKIO pin frequency.
3. The frequency of the peripheral clock (Pφ) is:
• The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL
circuit 1, and the division ratio of divider 1.
• The peripheral clock frequency should not be set higher than the frequency of the CKIO
pin, higher than 33.34 MHz, or lower than 13 MHz when the USB is used.
4. ×1, ×2, ×3, or ×4 can be used as the multiplication ratio of PLL circuit 1. ×1, ×1/2, ×1/3, or
×1/4 can be selected as the division ratios of divider 1. Set the rate in the frequency control
register.
5. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the
multiplication ratio of PLL circuit 1. Use the output frequency under 133.34 MHz.
Rev. 2.00, 09/03, page 278 of 690