HD6417705F133V Datasheet, PDF (67/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Classification Symbol
I/O
Bus control
CS0,
O
CS2 to CS4,
CS5A, CS5B,
CS6A, CS6B,
RD
O
RD/WR
O
BS
O
WE3
O
WE2
O
WE1
O
WE0
O
CKE
O
DQMUU
O
DQMUL
O
DQMLU
O
DQMLL
O
RASU
O
RASL
O
CASU
O
CASL
O
AH
O
WAIT
I
Name
Chip select 0,
2 to 4, 5A, 5B,
6A, 6B
Function
Chip-select signal for external
memory or devices.
Read
Indicates reading of data from
external devices.
Read/write
Read/write signal.
Bus start
Bus-cycle start.
Highest-byte
write
Indicates that bits 31 to 24 of the
data in the external memory or
device are being written.
Second-highest- Indicates that bits 23 to 16 of the
byte write
data in the external memory or
device are being written.
Second-lowest- Indicates that bits 15 to 8 of the
byte write
data in the external memory or
device are being written.
Lowest-byte
write
Indicates that bits 7 to 0 of the data
in the external memory or device
are being written.
CK enable
Clock enable. (SDRAM)
DQ mask UU Selects D31 to D24. (SDRAM)
DQ mask UL Selects D23 to D16. (SDRAM)
DQ mask LU Selects D15 to D8. (SDRAM)
DQ mask LL Selects D7 to D0. (SDRAM)
Row address U Specifies a row address. (SDRAM)
Row address L Specifies a row address. (SDRAM)
Column address Specifies a column address.
U
(SDRAM)
Column address Specifies a column address.
L
(SDRAM)
Address hold Address hold signal.
Wait
Inserts a wait cycle into the bus
cycles during access to the
external space.
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