HD6417705F133V Datasheet, PDF (695/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CKIO
A25 to A0
A12/A11*¹
Tr
Trw
Tc1
Tcw
Td1
Tde
Tap
t_AD1
t_AD1
t_AD1
Row address
Column address
t_AD1
t_AD1
t_AD1
Read A command
CSn
RD/WR
RASU/L
CASU/L
DQMxx
t_CSD1
t_RWD1
t_RASD1
t_RASD1
t_CASD1
t_CASD1
t_DQMD1
D31 to D0
BS
t_BSD
t_BSD
t_CSD1
t_RWD1
t_DQMD1
t_RDS2 t_RDH2
CKE
DACKn*²
t_DACD
(High)
t_DACD
Notes: 1. Address pin to be connected to A10 of SDRAM.
2. DACKn is a waveform when active-low is specified.
Figure 25.23 Synchronous DRAM Single Read Bus Cycle
(Auto Precharge, CAS Latency = 2, TRCD = 2 Cycle, TRP = 2 Cycle)
Rev. 2.00, 09/03, page 647 of 690