HD6417705F133V Datasheet, PDF (139/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

(1) TLB address array access
• Read access
31
24 23
17 16
12 1110 9 8 7 6
2 10
Address field 1 1 1 1 0 0 1 0 * ^{. . . . . . . . . . . .} *
VPN
* * W 0 * ^{. . . . . . . . .} * 00
31
Data field
VPN
17 16
12 1110 9 8 7
0
0 ^{. . . . . . .} 0 VPN 0 V
ASID
• Write access
31
24 23
17 16
12 1110 9 8 7 6
2 10
Address field 1 1 1 1 0 0 1 0 * ^{. . . . . . . . . . . .} *
VPN
* * W 0 * ^{. . . . . . . . .} * 00
31
Data field
VPN
17 16
12 1110 9 8 7
0
* ^{. . . . . . .} * VPN * V
ASID
VPN: Virtual page number
V: Valid bit
W: Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)
ASID: Address space identifier
*: Don't care bit
(2) TLB data array access
• Read/write access
31
24 23
17 16
12 1110 9 8 7
2 10
Address field 1 1 1 1 0 0 1 1 * ^{. . . . . . . . . . . .} *
VPN
* * W * ^{. . . . . . . . . . .} * 00
Data field
31 29 28
000
PPN
10 9 8 7 6 5 4 3 2 1 0
X V X PR SZ C D SH X
PPN: Physical page number
PR: Protection key field
C: Cacheable bit
SH: Share status bit
VPN: Virtual page number
X: 0 for read, don't care bit for write
W: Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)
V: Valid bit
SZ: Page-size bit
D: Dirty bit
*: Don't care bit
Figure 3.14 Specifying Address and Data for Memory-Mapped TLB Access
Rev. 2.00, 09/03, page 91 of 690