HD6417705F133V Datasheet, PDF (266/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

7.8.7 Bank Active
The synchronous DRAM bank function is used to support high-speed accesses to the same row
address. When the BACTV bit in SDCR is 1, accesses are performed using commands (READ,
WRIT) without auto-precharge. This function is called bank-active function. This function is valid
only for either the upper or lower bits of area 3. When area 3 is set to bank-active mode, area 2
should be set to normal space or byte-selection SRAM. When areas 2 and 3 are both set to
SDRAM or both the upper and lower bits of area 3 are connected to SDRAM, auto pre-charge
mode must be set. In this case, precharging is not performed when the access ends. When
accessing the same row address in the same bank, it is possible to issue the READ or WRIT
command immediately, without issuing an ACTV command. As synchronous DRAM is internally
divided into several banks, it is possible to activate one row address in each bank. If the next
access is to a different row address, a PRE command is first issued to precharge the relevant bank,
then when precharging is completed, the access is performed by issuing an ACTV command
followed by a READ or WRIT command. If this is followed by an access to a different row
address, the access time will be longer because of the precharging performed after the access
request is issued.
In a write, when auto-precharge is performed, a command cannot be issued for a period of Trwl +
Tpc cycles after issuance of the WRITA command. When bank active mode is used, READ or
WRIT commands can be issued successively if the row address is the same. The number of cycles
can thus be reduced by Trwl + Tpc cycles for each write.
There is a limit on t_RAS, the time for placing each bank in the active state. If there is no guarantee
that there will not be a cache hit and another row address will be accessed within the period in
which this value is maintained by program execution, it is necessary to set auto-refresh and set the
refresh cycle to no more than the maximum value of t_RAS.
A burst read cycle without auto-precharge is shown in figure 7.20, a burst read cycle for the same
row address in figure 7.21, and a burst read cycle for different row addresses in figure 7.22.
Similarly, a burst write cycle without auto-precharge is shown in figure 7.23, a single write cycle
for the same row address in figure 7.24, and a single write cycle for different row addresses in
figure 7.25.
When bank active mode is set, if only accesses to the respective banks in the area 3 space are
considered, as long as accesses to the same row address continue, the operation starts with the
cycle in figure 7.20 or 7.23, followed by repetition of the cycle in figure 7.21 or 7.24. An access to
a different area during this time has no effect. If there is an access to a different row address in the
bank active state, after this is detected the bus cycle in figure 7.22 or 7.25 is executed instead of
that in figure 7.21 or 7.24. In bank active mode, too, all banks become inactive after a refresh
cycle or after the bus is released as the result of bus arbitration.
Rev. 2.00, 09/03, page 218 of 690