HD6417705F133V Datasheet, PDF (354/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

b. Canceling sleep by power-on reset
CKIO
RESETP^*1
Reset
STATUS
Normal^*5
Sleep^*4 *2
Reset^*3
Normal^*5
0 to 10 Bcyc^*6
0 to 30 Bcyc^*6
Notes:
1. When the PLL1's multiplication ratio is changed by a power-on reset,
keep RESETP low during the PLL's oscillation settling time.
2. Undefined
3. Reset: HH (STATUS1 high, STATUS0 high)
4. Sleep: HL (STATUS1 high, STATUS0 low)
5. Normal: LL (STATUS1 low, STATUS0 low)
6. Bcyc: Bus clock cycle
Figure 11.8 Canceling Sleep by Power-On Reset STATUS Output
c. Canceling sleep by manual reset
Reset
CKIO
RESETM^*1
STATUS Normal^*4
Sleep^*3
Reset^*2
Normal^*4
0 to 80 Bcyc^*5
0 to 30 Bcyc^*5
Notes: 1. Keep RESETM low until STATUS becomes reset.
2. Reset: HH (STATUS1 high, STATUS0 high)
3. Sleep: HL (STATUS1 high, STATUS0 low)
4. Normal: LL (STATUS1 low, STATUS0 low)
5. Bcyc: Bus clock cycle
Figure 11.9 Canceling Sleep by Manual Reset STATUS Output
In Case of Hardware Standby:
Figures 11.10 and 11.11 show examples of pin timing in hardware standby mode.
The CA pin is sampled using EXTAL2 (32.768 kHz), and a hardware standby request is only
detected when the pin is low for two consecutive clock cycles.
The CA pin must be held low while the chip is in hardware standby mode.
Clock oscillation starts when the CA pin is driven high after the RESETP pin is driven low.
Rev. 2.00, 09/03, page 306 of 690