HD6417705F133V Datasheet, PDF (706/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CKIO
A25 to A0
A12/A11^*1
Tnop
Tc1
Tc2
Tc3
Tc4
t_AD1
t_AD1
t_AD1
t_AD1
t_AD1
t_AD1
Column
address
(1-4)
Write command
t_AD1
t_AD1
CSn
RD/WR
t_CSD1
t_RWD1
t_RWD1
RASU/L
CASU/L
DQMxx
D31 to D0
BS
t_CASD1
t_DQMD1
t_WDD2
t_WDH2
t_BSD
t_CSD1
t_RWD1
t_RASD1
t_CASD1
t_DQMD1
t_WDD2
t_WDH2
t_BSD
CKE
DACKn^*2
t_DACD
(High)
t_DACD
Notes: 1. Address pin to be connected to A10 of SDRAM.
2. DACKn is a waveform when active-low is specified.
Figure 25.34 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode: WRITE Command, Same Row Address,
TRCD = 1 Cycle, TRWL = 1 Cycle)
Rev. 2.00, 09/03, page 658 of 690