HD6417705F133V Datasheet, PDF (178/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

6.3.3 Interrupt Control Register 1 (ICR1)
ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ0 to
IRQ5 individually: rising edge, falling edge, high level, or low level.
Bit
Bit Name Initial Value R/W Description
15
MAI
0
R/W Mask All Interrupts
When set to 1, masks all interrupt requests when
a low level is being input to the NMI pin. Masks
NMI interrupts in standby mode.
0: All interrupt requests are not masked when a
low level is being input to the NMI pin
1: All interrupt requests are masked when a low
level is being input to the NMI pin
14
IRQLVL
1
R/W Interrupt Request Level Detect
Selects whether the IRQ3 to IRQ0 pins are
enabled or disabled to be used as four
independent interrupt pins. This bit does not
affect the IRQ4 and IRQ5 pins.
0: Used as four independent interrupt request
pins IRQ3 to IRQ0
1: Used as encoded 15-level interrupt pins as
to IRL3 IRL0
13
BLMSK
0
R/W BL Bit Mask
Specifies whether NMI interrupts are masked
when the BL bit of the SR register is 1.
0: NMI interrupts are masked when the BL bit is 1
1: NMI interrupts are accepted regardless of the
BL bit setting
12

0
R
Reserved
This bit is always read as 0. The write value
should always be 0.
Rev. 2.00, 09/03, page 130 of 690